Why does the Verilog testbench shows 'reg' for inputs & 'wire' for outputs while in the module we take 'reg' for outputs and 'wire' for inputs? - Quora
Image write module in Verilog. The output file image is stored in the... | Download Scientific Diagram
![38-1 Difference between REG and WIRE in verilog, their physical meaning,How to choose REG and WIRE - YouTube 38-1 Difference between REG and WIRE in verilog, their physical meaning,How to choose REG and WIRE - YouTube](https://i.ytimg.com/vi/bJnNIpiT2wQ/hqdefault.jpg)